Welcome
1.
Introduction
2.
Metrics and Evaluation
3.
Pipelining
4.
Branches
❱
4.1.
Prediction
4.2.
Branch Target Buffer
4.3.
Direction Predictor
4.4.
2 Bit Predictor
4.5.
History Based Predictors
4.6.
PShare
4.7.
Tournament Predictor
4.8.
Return Address Stack
5.
Predication
6.
Instruction Level Parallelism
❱
6.1.
False Dependencies
6.2.
What is ILP?
7.
Instruction Scheduling
❱
7.1.
Tomasulo's Algorithm - Issuing
7.2.
Tomasulo's Algorithm - Dispatching
7.3.
Tomasulo's Algorithm - Writing
7.4.
Tomasulo's Algorithm - Review
7.5.
Tomasulo's Algorithm - Load and Store
7.6.
Tomasulo's Algorithm - Timing
8.
Reorder Buffer
❱
8.1.
ROB In Depth
8.2.
Recovery
8.3.
ROB Timing
8.4.
Extra Topics
9.
Memory Ordering
❱
9.1.
Load-Store Queue
9.2.
OOO Load/Store Execution
9.3.
Summary
10.
Compiler ILP
❱
10.1.
Tree Height Reduction
10.2.
Instruction Scheduling
10.3.
Loop Unrolling
10.4.
Function Call Inlining
11.
VLIW
12.
Cache
13.
Virtual Memory
14.
Advanced Caches
Light (default)
Rust
Coal
Navy
Ayu
ROB Timing
Below are ROB timing quizzes and examples from the lecture.
ROB timing example
ROB timing quiz
